1. Field of the Invention
The present invention relates to the field of integrated circuit fabrication, particularly to a process for improving critical dimension uniformity for integrated circuit arrays.
2. Description of the Related Art
In the semiconductor industries, integrated circuit (IC) devices have become faster, smaller, and more efficient. This trend has continued with the development of fabrication technology to increase circuit densities on chips.
Reducing critical dimension is one important way to increase circuit densities. The critical dimension (CD) is the dimension of the smallest geometrical features (width of interconnect line, contacts, trenches, etc.) formed during semiconductor device manufacturing. Critical dimensions need to be reduced in order to facilitate the formation of smaller features and faster, more efficient circuits.
In fabricating certain IC devices with small CD, however, pattern non-uniformity occurs due to loading effects. Some IC devices have a number of identical circuit elements arranged in multiple arrays. Such IC devices are typically formed by simultaneously forming multiple arrays on a single semiconductor substrate. In arrays formed by certain methods, the inventors have found a tendency for edge portions to have different dimensions than central portions.